1. Field of the Invention
This invention is related to dynamic random access memory and more particularly this invention is related to methods and circuits to select and activate memory cells of the DRAM.
2. Description of the Related Art
The structure and function of a synchronized dynamic random access memory is described in the Joint Electron Device Engineering Council (JEDEC) standard 21-C section 3.11.5 release 4 and shown schematically in FIG. 1a. An array 100 of memory cells 105 is arranged in rows and columns. FIG. 1b illustrates the detail of the memory array 100. Each memory cell 105 consists of a capacitor C 105b and a pass transistor Mp 105a. The gate of each pass transistor is connected to one of the word-lines WL0, . . . , WLi 110 that form the rows of the array 100 of DRAM cells. The drain of the pass transistor Mp 105a is connected to a top plate of the capacitor C 105b. The bottom plate of the capacitor C 105b is connected commonly with all the bottom plates of the cell capacitors of the DRAM array to a reference voltage source. The source of the pass transistor Mp 105a is connected to one of the bit-lines BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120.
A digital data bit is stored as a quantum of electrical charge on the capacitor C 105b. To write or store the digital data bit to one of the memory cells 105, the bit-line BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120 containing the desired memory cell 105 is set to a voltage level indicating the logic state of a digital data bit The word-line WL0, . . . , WLi 110 is set to a voltage level sufficient to turn on the pass transistor Mp 105a and the capacitor C 105b is charged to the voltage level indicating the logic state of the digital data bit.
To read or fetch the digital data bit from the desired memory cell 105, the bit-line BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120 is precharged to a reference voltage Vref. The reference voltage Vref is generally one half the voltage level of the power supply voltage. The word-line WL0, . . . , WLi 110 containing the desired memory cell 105 is brought to the voltage level sufficient to activate the pass transistor Mp 105a. The charge present on the capacitor C 105b flows to the bit-line BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120 connected to the desired memory cell 105, if the desired memory cell 105 contains a digital data bit indicating a first logic state (1). The flow of charge from the capacitor C 105b increases the voltage level present on the bit-line BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120. However, if the capacitor C 105b is discharged, indicating the memory cell 105 contains a second logic state (0), charge will flow to the capacitor decreasing the voltage level on the bit-line BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120.
Returning now to FIG. 1a, the row digital address word RADD0, . . . , RADDk 125 is an input from external circuitry identifying the row location of the array 110 containing the desired memory cell 105. The digital address word RADD0, . . . , RADDk 125 is decoded by the row decoder to select the desired word-line WL0, . . . , WLi 110.
The column digital address word CADD0, . . . , CADDj 135 is a second input from external circuitry identifying the column location of the array 100 containing the desired memory cell 105. The column digital address word CADD0, . . . , CADDj 135 is decoded by the column decoder 140 to create the column select signals YAD0, . . . , YADm 145. One of the column select signals YAD0, . . . , YADm 145 is activated to select the column containing the desired memory cell 105.
The primary bit-lines BL00, . . . , BLmn 115 and the complementary bit-lines {overscore (BL00)}, . . . {overscore (BLmn)} 120 are pair-wise connected to one of the sense amplifiers 150. Each sense amplifier detects the change in voltage on one of the bit-lines BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120 that results from the presence or absence of charge present on the memory cell 105 indicating the logic state of the digital data bit. The sense amplifier is a positive feedback amplifier that detects the voltage difference between the primary bit-line BL00, . . . , BLmn 115 and complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120 and forces the primary bit-line BL00, . . . , BLmn 115 to the logic state of the memory cell 105 attached to it or the complementary logic state of the memory cell 105 if it is attached to the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120. Conversely, the sense amplifier forces the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120 to the complement logic state of the selected memory cell 105 connected to the primary bit-line BL00, . . . , BLmn 115. However, if the selected memory cell 105 is connected to the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120, the sense amplifier forces the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120 to the logic state of the selected memory cell 105.
A representative schematic of the sense amplifier 150 is shown in FIG. 1c. If the primary bit-line BL00, . . . , BLmn 115 is at a voltage greater than the voltage level of complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120, the N-type metal oxide semiconductor transistor (NMOS) M2 begins to conduct. This lowers the voltage present on the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120 toward the level of the power supply voltage source and begins to force P-type MOS transistor (PMOS) M3 to conduct. The primary bit-line BL00, . . . , BLmn 115 is then forced higher toward the voltage level of power supply voltage source VH. This positive feedback continues until the primary bit-line BL00, . . . , BLmn 115 has reached the voltage level of the power supply voltage source VH and the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120 has reached the level of the power supply voltage source VL. Alternately, if the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120 is at a voltage level larger than the voltage level on the primary bit-line BL00, . . . , BLmn BL00, . . . , BLmn, the NMOS transistor M1 begins to conduct lowering the voltage level of the primary bit-line BL00, . . . , BLmn 115 toward the power supply voltage source VL. This causes the PMOS transistor M4 to begin to conduct raising the voltage level of the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120 toward the power supply voltage source VH. As described above the positive feedback will ultimately force the primary bit-line BL00, . . . , BLmn 115 to the voltage level of the power supply voltage source VL and the complementary bit-line {overscore (BL00)}, . . . {overscore (BLmn)} 120 to the voltage level of the power supply voltage source VH.
During this sensing, amplification, and latching of the level of voltage present on the primary bit-line BL00, . . . , BLmn 115 and the complementary bit-line {overscore (BL00)}, . . . , {overscore (BLmn)} 120, a relatively large current flows from the power supply voltage source VH to the bit-lines BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120 and a relatively large current flows from the bit-lines BL00, . . . , BLmn 115 or {overscore (BL00)}, . . . {overscore (BLmn)} 120 to the power supply voltage source VL.
Returning to FIG. 1a, it is apparent that when one word-line WL0, . . . , WLi 110 is activated, the charge level present on each memory cell 105 of the row connected to the one word-line WL0, . . . , WLi 110 is conducted to the bit-lines BL00, . . . , BLmn 115 and {overscore (BL00)}, . . . {overscore (BLmn)} 120. Not all of the memory cells 105 on the selected word-line 110 are to be fetched or read during this cycle, but all the memory cells 105 on the selected word-line have to be restored to prevent loss of the digital data bits at the completion of the read cycle. This requires that all the sense amplifiers 150 attached to the array 100 be activated. Activating all the sense amplifiers 150 attached to an array creates a very large current surge from the power supply voltage source VH and into the power supply voltage source VL. In battery powered operations the power supply voltage source VH is the positive terminal of the battery and the power supply voltage source VL is the negative terminal of the battery. The large surge of current from activating all the sense amplifiers can cause damage to the battery.
The power supply voltage source VH and the power supply voltage source VL are connected to the sense amplifiers 150 through the PMOS transistor 156 and the NMOS transistor 158. The PMOS transistor 156 and the NMOS transistor 158 are turned on respectively by the global sense amplifier activation signals GSAP and GSAN. Multiple sense amplifiers 150 are grouped together 155 to allow simultaneous access to multiple memory cells 105. At the completion of the sensing, amplifying, and latching of the charge indicating the as digital data bits present in the memory cells 105 of the selected word-line 110, the desired column select line YAD0 of the column select lines YAD0, . . . , YADm 145 turns on the gating NMOS transistors 160 to transfer the logic state present on the desired set of bit-lines BL00, . . . , BLmn 115 and {overscore (BL00)}, . . . {overscore (BLmn)} 120 to the 40 bus 170. The I/O bus 170 will amplify and buffer the digital data bits to create the digital output word DQ0, . . . , DQX 175 for transfer to external circuitry.
The unselected column select lines YADm keep the transistor 165 connected to keep the undesired bit-lines BL00, . . . , BLmn 115 and {overscore (BL00)}, . . . {overscore (BLmn)} 120 disconnected from the I/O bus 170.
At the completion of the read cycle, the memory cells 105 are restored and the selected word-line 110 is deactivated. The column select lines YAD0, . . . , YADm 145 are all deactivated to isolate the sense amplifiers 150 and the bit-lines BL00, . . . , BLmn 115 and {overscore (BL00)}, . . . {overscore (BLmn)} 120 from the I/O bus 170. The global sense amplifier activation signals GSAN 157 and GSAP 159 are set to a voltage level that will turn off the NMOS transistor 158 and the PMOS transistor 156 to disconnect the sense amplifiers 150 from the power supply voltage source VL and the power supply voltage source VH. Prior to the subsequent operation, the bit-lines BL00, . . . , BLmn 115 and {overscore (BL00)}, . . . {overscore (BLmn)} 120 are precharged and equalized to a reference voltage Vref that is usually one half the voltage difference of the power supply voltage sources VH and VL. This precharge and equalization is accomplished by circuitry not shown in FIG. 1a. 
Refer now to FIG. 2 for a representative timing diagram of a read or fetch cycle of a synchronous DRAM. The timing control signals RAS, CAS and CLOCK are the external inputs of the SDRAM to the control circuitry 180 of FIG. 1a. At time t1, the RAS and CAS signals are at voltage levels indicating that the row address is received on the external address bus of a multiplexed address SDRAM. The row address is decoded to select the desired word-line as described above. At the time t2, the RAS and CAS signals are at voltage levels indicating the arrivals of the column digital address on the address bus. The bit-lines UBL/{overscore (UBL)} and SBL/{overscore (SBL)} are precharged prior to the beginning of the read cycle to the reference voltage Vref as described above. The select word-line is activated and the charge present on the memory cells begins to flow to the bit-lines. The global sense amplifier activation signals GSAP and GSAN are respectively brought to the power supply voltage sources VH and VL at time t3. The activation of the sense amplifiers forces the selected bit-lines SBL/{overscore (SBL)} and the unselected bit-lines UBL/{overscore (UBL)} simultaneously to the voltage levels of the power supply voltages VH and VL at time t4. This causes the surge of current into and out of the bit-lines as described above.
The column address is decoded to activate one of the column select lines YAD0, . . . , YADm as described above.
The JEDEC standard 21C on page 3.9.5-13 describes non-address multiplexed DRAM requirements. In this description the digital row address word is the high order bits of the input address bus and the digital column address word is the low order bits of the input address bus. The input address bus having both the digital row address word and the digital column address word allows an increase in performance of the SDRAM.
U.S. Pat. Nos. 5,719,815 and 5,862,095 (Takahashi et al.) teach methods and circuits to reduce consumed power within a DRAM by controlling the number of sense amplifier activated during a refresh operation versus the number of sense amplifier activated during a normal read and write operation.
U.S. Pat. No. 5,745,913 (Pattin et al.) describes a DRAM controller for a multiprocessing computer system. The DRAM controller prioritizes the flow of digital data to a bank of memory to maximize the amount of data transferred to a row of a memory array.
U.S. Pat. No. 5,778,447 (Kuddes) discloses a data processing system containing DRAM. The data processing system has a bus structure that automatically generates the row address strobe and column address strobe as well as other timing and control signals necessary to activate DRAM attached to the system bus. Additional signals are used to create the necessary timings and controls of non-DRAM circuitry attached to the system bus.
U.S. Pat. No. 5,642,326 (Sakurai et al.) describes a DRAM having a circuit for controlling the selection of the row decoder and the activation of the sense amplifiers with the externally provided row address strobe. The DRAM further has a word-line control circuit to provide the appropriate electrical voltage levels to activate the pass transistors of the memory cells attached to the word-line and to deactivate the pass transistors of the memory cells after the electrical charge has been sensed and amplified by the sense amplifiers. The DRAM further has thin gate oxide films designed to be subjected to lower voltage fields to improve reliability. The voltage levels of the word-lines are such that the need for leakage current compensation is eliminated. The DRAM, additionally, has reduced time to restore the charges to the memory cells attached to the selected word-lines subsequent to a read operation and a reduced cycle time required for a data writing operation.
U.S. Pat. No. 5,844,915 (Saitoh et al.) describes a method for determining the leakage current of a word-line in a DRAM. The level of the leakage current of the wordline of the DRAM is an indication of the adequacy of the performance of the DRAM and is used during testing subsequent to fabrication of the DRAM.
U.S. Pat. No. 5,457,659 (Schaefer) teaches a DRAM, which is adapted to provide extended data, output upon reception of appropriate logic signals. The DRAM includes a GAS before RAS detection circuit, which controls the output data during a CAS before RAS refresh cycle.
An object of this invention is to provide a DRAM having a minimum current surge during activation of bit-lines within the DRAM during a row address strobe cycle.
Another object of this invention is to prevent damage to a battery attached to a DRAM when the bit-lines of the DRAM are activated during a row address strobe cycle.
Further, another object of this invention is to minimize the current surge during activation of the bit-lines of the DRAM within a minimum of the time to access digital data retain within the DRAM array during a row address strobe cycle.
To accomplish these and other objects a decode circuit within a DRAM will receive a digital address word indicating column locations of a plurality of desired digital data bits retained within an array of DRAM memory cells, decode digital address word, and selectively activate bit-lines of the column locations of the plurality of desired digital data bits at a first time and activate all remaining bit-lines at times subsequent to the first time to minimize row address strobe cycle current. The decode circuit has a decode logic circuit to select one of the column locations that is designated by the digital address date word. The decode circuit additionally has a first timing circuit and at least one second timing circuit. The first timing circuit is connected between the decode logic circuit and the column locations of the array of DRAM cells to activate the selected one column location to be activated at the first time. The second timing circuit is connected between the logic circuit and the column locations of the DRAM cells to activate all unselected locations at times subsequent to the first time.
To facilitate the operation of the decode circuit the digital address word is received at a row address strobe time.